1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device with a thermally nitrided film on a high resistance film and a method of manufacturing the same.
2. Description of the Related Art
The fine patterning and high performance of a semiconductor device have still vigorously been developed. At present, a super high integration semiconductor device such as memory device and logic device has been developed to meet the design rule of 0.15 to 0.25 .mu.m.
In conjunction with such fine patterning and high performance of the semiconductor element, a fine multilayer wiring layer is indispensable to form a semiconductor device. For this purpose, the flat and smooth surface of an interlayer insulating film between the wiring layers is strongly required. Therefore, various insulating materials have been used for the interlayer insulating film. Also, the increase of film forming speed of such an interlayer insulating film also becomes important for the reduction of manufacturing cost of the semiconductor device.
A semiconductor device with a high resistance layer, for example, an SRAM is conventionally known in which the resistance value of the high resistance layer should be precisely controlled. In the progress of manufacturing technique of the semiconductor device, the resistance value is likely to fluctuate. This is because unnecessary impurities are easily introduced from the interlayer insulating film into the high resistance layer.
As conventional techniques to solve the above problems, there are known the technique disclosed in Japanese Examined Patent Disclosure (JP-B-5-16186: hereinafter, to be referred to as a first conventional example) and the technique disclosed in Japanese Examined Patent Disclosure (JP-B-6-91189: hereinafter, to be referred to as a second conventional example).
The techniques described in the above first conventional example of a manufacturing method of the semiconductor device will now be described with reference to the drawings. FIGS. 1A to 1E are cross sectional views of a semiconductor device in an order of the manufacturing process.
As shown in FIG. 1A, a field oxide (SiO.sub.2) film 102 and a gate oxide (SiO.sub.2) film 103 are formed in predetermined regions on a P-type single crystal Si substrate 101. Polysilicon layers 104 and 104a are formed on the films 102 and 103, respectively. A gate electrode of an MOS transistor is formed from the polysilicon layer 104a on the gate oxide film 103. Subsequently, the surfaces of the polysilicon layers 104 and 104a are thermally oxidized and a thermal oxidation film 105 is formed. An Si.sub.3 N.sub.4 film 106 is formed on the thermal oxidation film 105.
Next, as shown in FIG. 1B, a silicon oxide film is deposited on the whole surface of the Si.sub.3 N.sub.4 film 106 by a chemical vapor deposition (CVD) method, and unnecessary portions are removed by etching such that a mask insulating layer 107 is formed. Subsequently, ion implantation of phosphorus impurities or the like and heat treatment are executed to form N.sup.+ diffusion layers 108 and 109 and an N.sup.+ gate electrode 104a. The N.sup.+ diffusion layer 108 functions as a source or drain region of the MOS transistor. In these processes, a high resistance portion 110 is formed in the polysilicon layer 104. Also, a high density impurity is implanted into the polysilicon layer 104a functioning as a gate electrode.
Next, as shown in FIG. 1C, the Si.sub.3 N.sub.4 film 106 is removed such that an Si.sub.3 N.sub.4 film 106a is left under the mask insulating layer 107.
Next, as shown in FIG. 1D, a PSG film 111 is deposited to cover the whole surface of the thermal oxidation film 105, the mask insulating film 107 and the like and is smoothed. Subsequently, contact holes are formed through the insulating films laminated on the N.sup.+ diffusion layers 108 and 109. An Al wiring 112 which is connected to the N.sup.+ diffusion layers 108 and 109 and another Al wiring 113 which is connected to the other N.sup.+ diffusion layer 109 are formed, respectively.
As mentioned above, an MOS transistor is formed on the surface of the P-type Si single crystal substrate 101 and a high resistance layer composed of electrode portions of the N.sup.+ diffusion layers 109 and the high resistance portion 110 are formed on the field oxide film 102. The high resistance layer is used as a load resistor element.
Next, as shown in FIG. 1E, an interlayer insulating film 114 which covers the Al wirings 112 and 113 and the like is formed. Finally, the N+ diffusion layers 109 function as electrode portions of the load resistor element. The surface of the high resistance portion 110 is covered by the thermally oxidized silicon film 105 and the Si.sub.3 N.sub.4 film 106a.
The Si.sub.3 N.sub.4 film 106a prevents the phosphorus impurities from being diffused from the PSG film 111 into the high resistance portion 110 so that the resistance value of the high resistance layer is fluctuated.
Next, the second conventional example of the manufacturing method of a semiconductor device will now be described with reference to FIGS. 2A to 2D. FIGS. 2A to 2D are cross sectional views of the semiconductor device in the order of the manufacturing method.
Next, as shown in FIG. 2A, element isolation oxide films 202 are formed on the surface of a P-type silicon semiconductor substrate 201. Subsequently, a gate oxide film 203 is formed. Then, a gate electrode 204 is formed of polysilicon or the like. Subsequently, N-type impurity ions such as phosphorus impurities or the like are implanted and are thermally treated, so that source and drain diffusion layers 205 are formed. At the same time, a gate electrode 204 is also formed. Thereafter, a silicon oxide film 206 is deposited to cover the whole surface.
Next, as shown in FIG. 2B, a BPSG film 207 is deposited on the silicon oxide film 206 and is thermally treated, thereby the surface is flattened.
Next, as shown in FIG. 2C, a first silicon nitride film 208 is formed on the BPSG film 207. This first silicon nitride film is deposited by the CVD method to have the film thickness of 100 nm to 200 nm. A high resistance layer 209 is formed on the first silicon nitride film 208. The high resistance layer 209 is formed of a semiconductor thin film of silicon or the like. subsequently, a second silicon nitride film 210 is deposited on the whole surface by the CVD method.
Next, as shown in FIG. 2D, an interlayer insulating film 211 is formed. Then, contact holes are formed through the interlayer insulating film 211, the second silicon nitride film 210, the first silicon nitride film 208, BPSG film 207, the silicon oxide film 206, and the gate oxide film 203 by a photolithography technique and a dry etching technique. Wirings 212 are formed by filling the contact holes with conductive material.
Finally, a passivation film 213 is formed to cover the whole surface. The passivation film 213 is an insulating film such as a silicon nitride film or the like which is deposited by a plasma CVD method or the like.
According to the second embodiment, the high resistance layer 209 functions as a load resistor element of an SRAM. The high resistance layer 209 is perfectly sealed by the first silicon nitride film 208 and second silicon nitride film 210.
The first silicon nitride film 208 and the second silicon nitride film 210 prevent the impurity ions from being diffused from the film such as a BPSG film 207 to be flattened into the high resistance portion 110 so that the resistance value of the high resistance layer 209 is fluctuated. The silicon nitride film functions as a barrier against a hydrogen ion or atom entering the high resistance layer 209 and restrains fluctuation of the resistance value of the high resistance layer.
As mentioned above, a fine multilayer wiring layer is indispensable to form the semiconductor device. It is strongly required to flatten or smooth the interlayer insulating film between the wiring layers, and various insulating materials have been used for an interlayer insulating film. When the interlayer insulating film is deposited on the wiring layer by the plasma CVD method, it is necessary to form the interlayer insulating film by a high density plasma CVD method for the purpose of reduction of the process time.
In consideration of the above circumstances, according to the first conventional example of the manufacturing method of a semiconductor device, the surface of the high resistance portion 110 is covered by the thermally oxidized silicon film 105 and the Si.sub.3 N.sub.4 film 106a is formed on the film 105. Therefore, change of the resistance value of the high resistance portion 110 after the interlayer insulating film is deposited by the high density plasma CVD method cannot be avoided. The change or fluctuation of the resistance value is caused by hydrogen atoms or hydrogen ions generated by the high density plasma CVD method and passing through the thermally oxidized silicon film 105 into the high resistance portion 110.
In case of the first conventional example, it has been confirmed in an examination by the inventor that a quantity of hydrogen atoms or ions contained in the high resistance portion 110 increases from 6.times.10.sup.18 atoms/cc to 1.times.10.sup.19 atoms/cc when the interlayer insulating film is deposited by the high density plasma CVD method.
In the second conventional example, the surface of the high resistance layer 209 is covered by the silicon nitride film which is deposited by the CVD method. Therefore, a large amount of uncontrollable interfacial energy levels are formed at the interface between the high resistance layer and the silicon nitride film. Such interfacial energy levels change a conductivity of the surface of the high resistance layer to increase the resistance value variation of the high resistance layer built in the semiconductor device such as an SRAM. A manufacturing yield of the semiconductor device decreases.
The problems as mentioned above are more typical when a high density and high performance of semiconductor device is realized.